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Register renaming
Results: 28

#	Item
21	Software Pipelining for (i=1, i<100, i++) { An alternative method of reorganizing loops Add to Reading List Source URL: homepage.cs.uiowa.edu Language: English - Date: 2006-03-28 11:52:24 Central processing unit Classes of computers Register renaming Software pipelining CPU cache Branch predictor Microarchitecture Reduced instruction set computing Pentium Pro Computer architecture Computer hardware Computer engineering
22	Energy-Performance Design Space Exploration in SMT Architectures Exploiting Selective Load Value Predictions A. Gellert1 G. Palermo2 Add to Reading List Source URL: webspace.ulbsibiu.ro Language: English - Date: 2010-02-24 17:04:56 Central processing unit Branch predictor CPU cache Microarchitecture Memory-level parallelism Register renaming Superscalar DEC Alpha Computer performance Computer architecture Computer hardware Computer engineering
23	E C E N[removed] Add to Reading List Source URL: lgjohn.okstate.edu Language: English - Date: 2008-01-11 17:17:26 Circular buffer Computer programming Software engineering Software bugs Register renaming Computing Re-order buffer Pointer
24	Computer Science 246 Computer Architecture Spring 2013 Add to Reading List Source URL: www.eecs.harvard.edu Language: English - Date: 2013-02-28 10:17:41 Electronic engineering Register renaming Processor register Tomasulo algorithm Register file Instruction set Out-of-order execution Computer architecture Computer engineering Central processing unit
25	The Alpha[removed]Microprocessor Architecture R. E. Kessler, E. J. McLellan1, and D. A. Webb Compaq Computer Corporation Add to Reading List Source URL: h18004.www1.hp.com Language: English - Date: 1999-11-05 17:26:28 Central processing unit Alpha 21264 CPU cache Branch predictor Microarchitecture Register renaming Instruction pipeline Alpha 21164 Superscalar Computer architecture Computer hardware Computer engineering
26	The Design Space of Shelving Dezs Sima Institute of Informatics, Kandó Polytechnic Budapest, 19 Nagyszombat utca, 1034 Budapest, Add to Reading List Source URL: www.wlu.ca Language: English - Date: 2012-03-14 16:49:25 Parallel computing Shelving buffer Superscalar Register renaming Instruction window Central processing unit POWER1 R10000 Reservation stations Computer architecture Computing Computer engineering
27	MICROPROCESSOR REPORT MIPS R10000 Uses Decoupled Architecture Add to Reading List Source URL: www.cs.cmu.edu Language: English - Date: 1997-10-06 18:42:23 R10000 MIPS architecture Out-of-order execution CPU cache Register renaming R4000 UltraSPARC Register file Reduced instruction set computing Computer hardware Computer architecture Computer engineering
28	PDF Document Add to Reading List Source URL: pages.cs.wisc.edu Language: English - Date: 2007-06-06 02:45:14 Central processing unit Compiler optimizations Parallel computing Vectorization Classes of computers CPU cache Register renaming Memory disambiguation Superscalar Computing Computer architecture Computer engineering